Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E' center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degr...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Online Access: | View Fulltext in Publisher |