| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === In this thesis, we firstly fabricated Al2O3/GeO2/Ge MOS capacitors. Al2O3 was deposited by atomic layer deposition (ALD), while GeO2 was formed by rapid thermal oxidation (RTO). The effect of forming gas annealing (FGA) at 300 °C for 30 min on MOS capacitors is investigated. Conductance method is utilized to extract the density of interface states of MOS capacitors. Besides, we discuss effect of constant voltage stress (CVS) and charge trapping behavior on N-Ge MOS capacitors.
Secondly, in order to enhance the thermal stability of nickel germanide (NiGe), a thin Pt layer was deposited between Ni and N-type Ge substrate to fabricate Schottky junction. With the help of atomic force microscopy (AFM) and scanning electron microscopy (SEM), it is found that the process window of NiGe film can be indeed enlarged by Pt incorporation. Moreover, the NiGe:Pt/N-Ge junction with RTA performed at 550 °C exhibits good electrical characteristics, including the lowest ideality factor (n) of 1.064, highest Schottky barrier height for electron (bn) of 0.579 eV, highest ION/IOFF ratio of 8.5104, and lowest series resistance (rs) of 11.11 . As a result, Ge Schottky PMOSFET (LG = 5 m) with NiGe:Pt was fabricated with alloy formed at 550 °C. After FGA treatment, a high drive-current of 33.5 μA/μm at VGS-VT = -2.4 V and VDS = -2 V was obtained. The drive-current is also higher than that of Ge PMOSFETs with NiGe and Pt2Ge3 S/D. Besides, an excellent subthreshold swing of 144 mV/dec is also demonstrated.
Finally, Ge channel NMOSFETs (LG = 4 m) with epitaxial GexSi1-x elevated S/D on GeOI substrate was fabricated. Elevated S/D efficiently enlarges the contact area and thus leads to lower series resistance in S/D (RSD). The drive-current at VG-VT = 2.8 V and VD = 2 V can be enhanced from 4.48 A/m for the NMOSFET with Ge S/D to 5.99 A/m for the NMOSFET with Ge0.95Si0.05 elevated S/D. In other words, approximately 33 % improvement in performance is achieved.
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