| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 99 === Matrix multiplication is a fundamental and important operation in many research and engineering problems. Enhancing matrix multiplication parallelism in a 2-dimensional PE (processing element) array is a popular approach to improve the computation efficiency. However, as the size of PE array increases, the multiplier reliability degrades.
This thesis proposes a coarse-grained reconfigurable PE array architecture to improve the reliability of a Canon matrix multiplier that utilizes a 2D PE array. Three fault tolerance schemes are proposed in this thesis. The first scheme bypasses the faulty PE’s and allocates the desired PE array size to achieve the given multiplication; this also enables one to multiply smaller matrices with a large PE array. The second scheme achieves graceful degradation. The work associated with a faulty PE is performed by its adjacent fault-free PE; this, in practice, also allows one to perform large matrix multiplication in a small PE array. The last hybrid scheme combines the previous two; it provides the best flexibility in terms of fault tolerance and computation efficiency.
Based on the Canon’s algorithm, we implement the proposed fault-tolerant reconfigurable multiplier as well as the software components that compute the PE array configurations and generate the execution sequences for each PE elements.
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