Showing 1 - 20 results of 35 for search '黃俊郎', query time: 0.41s Refine Results
  1. 1
    子游學案
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  2. 2
    子游學案
    by Huang, Zun-Lang, 黃俊郎
    Published 1968
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  3. 3
    Simulation-Based Test Patterns to Program Converter for Software-Based Self-Test
    by Yu-Hsiang Chang, 章宇翔
    Published 2019
    Other Authors: “...黃俊郎...”
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  4. 4
    Evaluation of an ADC BIST Technique Using Statistical Simulation
    by Yi-Ren Chen, 陳奕任
    Published 2004
    Other Authors: “...黃俊郎...”
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  5. 5
    Deterministic Parallel ATPG Techniques to Meet Diverse Test Generation Requirements
    by Kuen-Wei Yeh, 葉琨煒
    Published 2017
    Other Authors: “...黃俊郎...”
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  6. 6
    Ray-Tracing Technique using Two-Stage Shortest Path Algorithm
    by Chun-Yu Shih, 施俊宇
    Published 2017
    Other Authors: “...黃俊郎...”
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  7. 7
    Implementation of Aging-Effect-Aware Path Delay Analysis
    by Yi-Yen Li, 李宜諺
    Published 2019
    Other Authors: “...黃俊郎...”
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  8. 8
    Software-Based Self-Test for Aging Defect Detection
    by Tzu-Hsiang Lin, 林子翔
    Published 2018
    Other Authors: “...黃俊郎...”
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  9. 9
    A High-Resolution FPGA Formatter with Symbol-Stretching and Inversion Capability
    by Chih-Lung Hsiao, 蕭智隆
    Published 2016
    Other Authors: “...黃俊郎...”
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  10. 10
    Test Data Volume and Power Management for Scan-Based At-Speed Testing
    by Yi-Tsung Lin, 林易增
    Published 2017
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  11. 11
    Design and Implementation of 25-ps Resolution, EG-Pool Based Formatter on FPGA
    by Kuan-Te Li, 李冠德
    Published 2016
    Other Authors: “...黃俊郎...”
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  12. 12
    Reducing Test Pattern Count by A Parallel N-pattern Compaction ATPG
    by Bo-Yi Li, 李柏毅
    Published 2018
    Other Authors: “...黃俊郎...”
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  13. 13
    Compression-aware Automatic Test Pattern Generationbased on Skew Insertion Technique in the Broadcast Environment
    by Chien-Ju Lin, 林建儒
    Published 2010
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  14. 14
    SOC Test Scheduling Using Sequence-Pair Representation
    by Chih-Chiang Huang, 黃志強
    Published 2005
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  15. 15
    方東樹文論研究
    by 金鎬
    Published 1997
    Other Authors: “...黃俊郎...”
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  16. 16
    A Cell Modeling Technique for Accurate IR-Drop Analysis
    by Hsin-Chieh Pan, 潘信傑
    Published 2010
    Other Authors: “...黃俊郎...”
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  17. 17
    A Design-for-Test Technique for Flat Panel Display Source Driver ICs
    by Shih-Hsuan Lin, 林士軒
    Published 2012
    Other Authors: “...黃俊郎...”
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  18. 18
    An NoC Router Design with Built-In Self-Test and Fault Tolerance Mechanism
    by Chien-Hsing Li, 李建興
    Published 2011
    Other Authors: “...黃俊郎...”
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  19. 19
    A Deterministic Parallel ATPG for Shared-Memory Multi-Core Systems
    by Chun-Hao Chang, 張峻豪
    Published 2011
    Other Authors: “...黃俊郎...”
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  20. 20
    Fault Tolerant Design for Large Scale Matrix Multiplier Based on Reconfigurable Architecture
    by Bo-Yu Jan, 詹博宇
    Published 2011
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