Mismatch Address Index Encoding for Data Compression in Scan Test

• Main Authors: Hcc-Hang Jang, 章恒嘉
• Other Authors: 曾王道
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/80749659924663809303

碩士 === 元智大學 === 資訊工程學系 === 95 === During the last decade, as the VLSI technology grows up, high performance, low-cost, high density integrated circuits became main stream. Hence, testing for integrated circuit is more and more complex. For example, augmentation of test data, prolonged test time, high energy consumption and bandwidth restriction of ATE (automatic test equipment) , will lift cost of testing. Thus test data compression is one of most often used methods to solve technical bottleneck; besides reducing test data effectively, it increases the speed of transmission to chip by ATE, and makes full use of limited bandwidth and memory of ATE. This Paper presents a new test-data compression technique that uses mismatch address index encoding. The main skill of this compress method, which transfers compressed test data to chip, records mismatch address of sorted test data. Experimental results for mismatch address index encoding has average compress ratio 82 percent which is higher than FDR and ARL encoding.