Showing 1 - 20 results of 25 for search '曾王道', query time: 0.14s Refine Results
  1. 1
    Design for Testability and Test Strategies of Multichip Modules
    by Wang-Dauh Tseng, 曾王道
    Published 1999
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  2. 2
    Design for diagnosability and diagnostic strategies of VLSI/WSI parallel architectures
    by Zeng, Wang-Dao, 曾王道
    Published 1993
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  3. 3
    Test Time and Test volume Reduction by Test Data Sharing
    by Chien-Wei Shih, 石健瑋
    Published 2008
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  4. 4
    Segmented LFSR for Deterministic Test Generations
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  5. 5
    A Low-Cost Self-Test Structure for SoC Interconnect Crosstalk Faults
    by 簡才富
    Published 2003
    Other Authors: “...曾王道...”
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  6. 6
    Low Power Test Pattern Generation
    by Chien-Feng Liao, 廖健峰
    Published 2009
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  7. 7
    Test Data Compression Based on Dictionary Grouping
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  8. 8
    Dual Linear Feedback Shift Register for Low Power BIST
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  9. 9
    Hybrid Run-Length and Pattern Run-Length for Test Data Compression
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  10. 10
    Pattern-Coupling-LFSR for Test Data Compression
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  11. 11
    Slice Test Data Compression
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  12. 12
    Test Data Compression Using Scan Chain Compaction and Broadcasting Scheme
    by Sung-Wei Cheng, 鄭松瑋
    Published 2009
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  13. 13
    Test Pattern Generation for Capture Power Reduction
    by Yen-Po Tseng, 曾彥博
    Published 2007
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  14. 14
    Structural Don’t Care Bits Filling for Peak Power Minimization During Scan Testing
    by Wei-jung Chiang, 江威融
    Published 2007
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  15. 15
    Mismatch Address Index Encoding for Data Compression in Scan Test
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  16. 16
    Test Data Compression Using Fixed Pattern Run-Length Coding
    by Tsu-Chi Tsai, 蔡賜錡
    Published 2009
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  17. 17
    Data Compression for Multiple Scan Slices Using Slice Run Length
    by Cheng-Chi Yang, 楊正旗
    Published 2009
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  18. 18
    Don’t Care Bits Filling for Reducing Capture Power
    by Chun-Kai Hsu, 許淳凱
    Published 2006
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  19. 19
    Test Time and Test Power Reduction for Multi-Scan Circuits based on Scan Cell Reordering
    by You-Liang Chen, 陳祐良
    Published 2006
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  20. 20
    Power Reduction for Circuit Under Testing Based on Test Vector Reordering
    by Chia-Ching Tsai, 蔡佳青
    Published 2006
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