Structural Don’t Care Bits Filling for Peak Power Minimization During Scan Testing
碩士 === 元智大學 === 資訊工程學系 === 95 === Power dissipation has become an important issue in VLSI design and testing. Especially in Scan-based architectures are expensive in power consumption during scanning in test vectors to the circuit. In the scan based circuit, the spurious transitions will be produced...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/17076422430582588169 |