| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 94 === For a full-scan sequential circuit testing, the power dissipation is almost occurred during the scan shift and capture operations. It is due to the high level of switching activity increased during this period. In this dissertation, we approach a multiple capture method to reduce the peak power consumption as well as average power consumption during testing. The basic idea of our approach is to divide a scan chain into a number of sub-scan chains, and only one sub-scan chain will be enabled at a time during the scan shift or capture operations. To efficiently deal with the “capture violation problem” during the capture operation, we develop a test pattern insertion method to solve this problem. Although this method can successfully deal with the capture violation problem, it increases the test application time greatly because a large amount of new test patterns are required to included in the original test set. In order to improve the test application time, a novel scan chain partition method by exploiting don’t care bits and a test pattern ordering approach are developed to reduce the test application time. The proposed approach can easily be implemented for any large full-scan sequential circuits. Experimental results for large ISCAS’89 benchmark circuits show that the proposed approach can efficiently reduce the peak power and average power dissipation during testing.
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