Reduction of Test Power during Test Application in Full-Scan Sequential Circuits with Multiple Capture Techniques
碩士 === 元智大學 === 資訊工程學系 === 94 === For a full-scan sequential circuit testing, the power dissipation is almost occurred during the scan shift and capture operations. It is due to the high level of switching activity increased during this period. In this dissertation, we approach a multiple capture me...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21160252328135397634 |