| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === In the IC design process, verification usually accounts for 70% ~ 80% times of the whole design procedure and has become the main design bottleneck[2]. In general, the IC design process starts with high level computer language like C/C++ which are then transformed into RTL (Register-Transfer Level) code. In the transformation, programming errors, called bugs, will be propagated and hid more deeply in the bulk codes and this bug-propagation makes debug more difficult in the future verification procedure.
In this thesis, we propose a verification pattern generation method which ensures the C/C++ program quality and thus lowers the debug cost in the succeeding design stages. In this thesis, we propose a simulation-based verification pattern generation technique for image codec. To guarantee the correctness of their image codec, the designers usually use pictures like Lena as the verification pattern. However, the verification quality is not guaranteed. To resolve this problem, the proposed pattern generation technique synthesizes the verification pattern according to a pre-defined block template. Compared to past approaches, e.g., Lena or random pictures, the proposed technique has two advantages. First, with much less pattern size (less than 20 vs. more than 2,000 blocks), better or the same code coverage figures are achieved. Second, the proposed method allows the user to specify the desired coverage profile to better fit his or her verification goal.
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