Simulation-Based Verification Pattern Generation for Image Processing Codec
碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === In the IC design process, verification usually accounts for 70% ~ 80% times of the whole design procedure and has become the main design bottleneck[2]. In general, the IC design process starts with high level computer language like C/C++ which are then transform...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26463450690897862542 |