VLSI Implementations of High-Speed Signed RNS Multipliers
碩士 === 逢甲大學 === 資訊工程研究所 === 85 === This thesis presents a high-speed signed residue number system (RNS) multiplier which is derived from the early works of unsigned RNS multipliers. The residue arithmetic function unit has high-speed comp...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29748692617071208737 |