A Computationally Efficient Compact Model for Trap-Assisted Carrier Transport Through Multi-Stack Gate Dielectrics of HKMG nMOS Transistors
This paper analyzes in detail the carrier transport through the multi-stack gate dielectrics of high-K metal gate (HKMG) nMOS transistors under different gate biases and temperatures. The existing uncertainty about the carrier transport mechanisms for different gate biases is resolved through accura...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2018-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8468030/ |