Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

• Main Authors: Huei Chaeng Chin, Cheng Siong Lim, Weng Soon Wong, Kumeresan A. Danapalasingam, Vijay K. Arora, Michael Loong Peng Tan
• Format: Article
• Language: English
• Published: Hindawi Limited 2014-01-01
• Series: Journal of Nanomaterials
• Online Access: http://dx.doi.org/10.1155/2014/879813

Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.