Energy/Delay Tradeoffs in All-Spin Logic Circuits

by Zhaoxin Liang, Sachin S. Sapatnekar
Published 2016-01-01

Performance Characterization and Majority Gate Design for MESO-Based Circuits

by Zhaoxin Liang, Meghna G. Mankalale, Jiaxi Hu, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar
Published 2018-01-01

CoMET: Composite-Input Magnetoelectric- Based Logic Technology

by Meghna G. Mankalale, Zhaoxin Liang, Zhengyang Zhao, Chris H. Kim, Jian-Ping Wang, Sachin S. Sapatnekar
Published 2017-01-01

A Comparative Study Between Spin-Transfer-Torque and Spin-Hall-Effect Switching Mechanisms in PMTJ Using SPICE

by Ibrahim Ahmed, Zhengyang Zhao, Meghna G. Mankalale, SACHIN S. Sapatnekar, Jian-Ping Wang, Chris H. Kim
Published 2017-01-01

Evaluation of Operating Margin and Switching Probability of Voltage- Controlled Magnetic Anisotropy Magnetic Tunnel Junctions

by Jeehwan Song, Ibrahim Ahmed, Zhengyang Zhao, Delin Zhang, Sachin S. Sapatnekar, Jian-Ping Wang, Chris H. Kim
Published 2018-01-01

A DNA Read Alignment Accelerator Based on Computational RAM

by Zamshed I. Chowdhury, Masoud Zabihi, S. Karen Khatamifard, Zhengyang Zhao, Salonik Resch, Meisam Razaviyayn, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
Published 2020-01-01

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

by Masoud Zabihi, Arvind K. Sharma, Meghna G. Mankalale, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Salonik Resch, Ulya R. Karpuzcu, Jian-Ping Wang, Sachin S. Sapatnekar
Published 2020-01-01