Improved state integrity of flip-flops for voltage scaled retention under PVT variation
Through measurements from 82 test chips, each with a state retention block of 8192 flip-flops, implemented using 65-nm design library, we demonstrate that state integrity of a flip-flop is sensitive to process, voltage, and temperature (PVT) variation. It has been found at 25?C that First Failure Vo...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
2013-04-02.
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| Subjects: | |
| Online Access: | Get fulltext |