Synchronization Overhead in SOC Compressed Test

Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this...

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Bibliographic Details
Main Authors: Gonciari, Paul Theo (Author), Al-Hashimi, Bashir (Author), Nicolici, Nicola (Author)
Format: Article
Language:English
Published: 2005-01.
Subjects:
Online Access:Get fulltext
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100 1 0 |a Gonciari, Paul Theo  |e author 
700 1 0 |a Al-Hashimi, Bashir  |e author 
700 1 0 |a Nicolici, Nicola  |e author 
245 0 0 |a Synchronization Overhead in SOC Compressed Test 
260 |c 2005-01. 
856 |z Get fulltext  |u https://eprints.soton.ac.uk/259335/1/pgonciari-tvlsi04.pdf 
520 |a Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-a-chip. This paper analyzes the sources of synchronization overhead and discusses the different trade-offs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case. 
655 7 |a Article