Testability Trade-offs for BIST Data Paths

by Nicolici, Nicola, Al-Hashimi, Bashir M.
Published 2004

Power Profile Manipulation: A New Approach for Reducing Test Application Time Under Power Constraints

by Rosinger, Paul, Al-Hashimi, Bashir, Nicolici, Nicola
Published 2002

Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction

by Rosinger, Paul, Al-Hashimi, Bashir, Nicolici, Nicola
Published 2004

Synchronization Overhead in SOC Compressed Test

by Gonciari, Paul Theo, Al-Hashimi, Bashir, Nicolici, Nicola
Published 2005

Variable-Length Input Huffman Coding for System-on-a-Chip Test

by Gonciari, Paul Theo, Al-Hashimi, Bashir, Nicolici, Nicola
Published 2003