A robust high speed serial PHY architecture with feed-forward correction clock and data recovery
This paper describes a robust architecture for high speed serial links for embedded SoC applications, implemented to satisfy the 1.5 Gb/s and 3 Gb/s Serial-ATA PHY standards. To meet the primary design requirements of a sub-system that is very tolerant of device variability and is easy to port to sm...
| Main Authors: | , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
2009-07.
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| Subjects: | |
| Online Access: | Get fulltext |