Probabilistic timing verification and timing analysis for synthesis of digital interface controllers
In this dissertation we present two techniques on the topic of digital interface design: a probabilistic timing verification and a timing analysis for synthesis, both rooted in a formal specification. Interface design arises when two digital components (e.g., a processor and a memory device) are to...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | English en |
| Published: |
2017
|
| Subjects: | |
| Online Access: | https://dspace.library.uvic.ca//handle/1828/8550 |