Performance and Power Optimizations for Highly Reliable Caches
This thesis introduces performance and power optimization techniques for caches. Our optimization techniques target both conventional caches, which are implemented using six-transistor (6T) cells, and highly reliable caches implemented using eight-transistor (8T) cells. In 6T cell caches, we enhanc...
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| Language: | English en |
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2013
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| Online Access: | http://hdl.handle.net/1828/5029 |