AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST

In this thesis, I/O signal recognizers, called VIRTUALBLOCKS, are synthesized to interface with a SYSTEM UNDER TEST (SUT). Methods for automated synthesis of virtualblocks allow us to simulate environment interfaces with SUT and also perform fault detection on SUT. Such methods must be able to recog...

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Main Author: She, Andrew Hai Liang
Format: Others
Published: UKnowledge 2004
Subjects:
Online Access:http://uknowledge.uky.edu/gradschool_theses/251
http://uknowledge.uky.edu/cgi/viewcontent.cgi?article=1254&context=gradschool_theses
id ndltd-uky.edu-oai-uknowledge.uky.edu-gradschool_theses-1254
record_format oai_dc
spelling ndltd-uky.edu-oai-uknowledge.uky.edu-gradschool_theses-12542015-04-11T05:05:11Z AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST She, Andrew Hai Liang In this thesis, I/O signal recognizers, called VIRTUALBLOCKS, are synthesized to interface with a SYSTEM UNDER TEST (SUT). Methods for automated synthesis of virtualblocks allow us to simulate environment interfaces with SUT and also perform fault detection on SUT. Such methods must be able to recognize incoming sequences of signals from SUT, and upon the signal recognition determine the proper outgoing sequences of signals to SUT. We characterize our systems into four distinctive systems: system under test, AUXILIARY SYSTEM, controller and external environment. The auxiliary system is represented as a form of condition system Petri net (virtualblocks) and interacts with SUT along with the interaction among the controller and the external environment. Fault detection is performed by subsystems called DETECTBLOCKS synthesized from the virtualblocks. We present construction procedures for virtualblocks andamp; detectblocks and discuss the notion of LEGALITY and DETECTABILITY. Finally, we illustrate our approach using a model of a scanner control unit. 2004-01-01T08:00:00Z text application/pdf http://uknowledge.uky.edu/gradschool_theses/251 http://uknowledge.uky.edu/cgi/viewcontent.cgi?article=1254&context=gradschool_theses University of Kentucky Master's Theses UKnowledge Auxiliary System|Petri Nets|Fault Detection|Condition Systems|System Under Test
collection NDLTD
format Others
sources NDLTD
topic Auxiliary System|Petri Nets|Fault Detection|Condition Systems|System Under Test
spellingShingle Auxiliary System|Petri Nets|Fault Detection|Condition Systems|System Under Test
She, Andrew Hai Liang
AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST
description In this thesis, I/O signal recognizers, called VIRTUALBLOCKS, are synthesized to interface with a SYSTEM UNDER TEST (SUT). Methods for automated synthesis of virtualblocks allow us to simulate environment interfaces with SUT and also perform fault detection on SUT. Such methods must be able to recognize incoming sequences of signals from SUT, and upon the signal recognition determine the proper outgoing sequences of signals to SUT. We characterize our systems into four distinctive systems: system under test, AUXILIARY SYSTEM, controller and external environment. The auxiliary system is represented as a form of condition system Petri net (virtualblocks) and interacts with SUT along with the interaction among the controller and the external environment. Fault detection is performed by subsystems called DETECTBLOCKS synthesized from the virtualblocks. We present construction procedures for virtualblocks andamp; detectblocks and discuss the notion of LEGALITY and DETECTABILITY. Finally, we illustrate our approach using a model of a scanner control unit.
author She, Andrew Hai Liang
author_facet She, Andrew Hai Liang
author_sort She, Andrew Hai Liang
title AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST
title_short AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST
title_full AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST
title_fullStr AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST
title_full_unstemmed AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST
title_sort automated synthesis of virtualblocks for interfacing system under test
publisher UKnowledge
publishDate 2004
url http://uknowledge.uky.edu/gradschool_theses/251
http://uknowledge.uky.edu/cgi/viewcontent.cgi?article=1254&context=gradschool_theses
work_keys_str_mv AT sheandrewhailiang automatedsynthesisofvirtualblocksforinterfacingsystemundertest
_version_ 1716800885546287104