Architectural Synthesis of a Coarse-Grained Run-Time-Reconfigurable Accelerator for DSP Applications

Given all its merits and potential, Reconfigurable Computing has attracted lots of research work. Reconfiguration costs as well as new Reconfigurable Computing specific challenges have so far been the main obstacles hindering reaching optimal reconfigurable computing solutions. Because of the flexib...

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Bibliographic Details
Main Author: Obeid, Abdulfattah Mohammad
Format: Others
Language:English
English
en
Published: 2006
Online Access:https://tuprints.ulb.tu-darmstadt.de/668/1/ObeidDissG_Part1v2.pdf
https://tuprints.ulb.tu-darmstadt.de/668/2/ObeidDissG_Part2_3.pdf
Obeid, Abdulfattah Mohammad <http://tuprints.ulb.tu-darmstadt.de/view/person/Obeid=3AAbdulfattah_Mohammad=3A=3A.html> (2006): Architectural Synthesis of a Coarse-Grained Run-Time-Reconfigurable Accelerator for DSP Applications.Darmstadt, Technische Universität, [Online-Edition: http://elib.tu-darmstadt.de/diss/000668 <http://elib.tu-darmstadt.de/diss/000668> <official_url>],[Ph.D. Thesis]