Dynamic stability margin analysis on SRAM
In the past decade, aggressive scaling of transistor feature size has been a primary force driving higher Static Random Access Memory (SRAM) integration density. Due to the scaling, nanometer SRAM designs are getting more and more stability issues. The traditional way of analyzing stability is the S...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2722 http://hdl.handle.net/1969.1/ETD-TAMU-2722 |
| Summary: | In the past decade, aggressive scaling of transistor feature size has been a primary
force driving higher Static Random Access Memory (SRAM) integration density. Due to
the scaling, nanometer SRAM designs are getting more and more stability issues. The
traditional way of analyzing stability is the Static Noise Margins (SNM). However, SNM
has limited capability to capture critical nonlinearity, so it becomes incapable of
characterizing the key dynamics of SRAM operations with induced soft-error. This thesis
defines new stability margin metrics using a system-theoretic approach. Nonlinear system
theories will be applied rigorously in this work to construct new stability concepts. Based
on the phase portrait analysis, soft-error can be explained using bifurcation theory. The
state flipping requires a minimum noise current (Icritical) and time (Tcritical). This work
derives Icritical analytically for simple L1 model and provides design insight using a level
one circuit model, and also provides numerical algorithms on both Icritical and Tcritial for
higher a level device model. This stability analysis provides more physical
characterization of SRAM noise tolerance property; thus has potential to provide needed
yield estimation. |
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