Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation

Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. This dissertation presents the decoder architectures for regular and irregular LDPC codes that provide substantial gains over existing academic and...

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Bibliographic Details
Main Author: Gunnam, Kiran Kumar
Other Authors: Choi, Gwan S.
Format: Others
Language:en_US
Published: 2010
Subjects:
low-density parity-check (LDPC) codes
offset min-sum
parallel processing
vector processing
decoder architecture
layered decoding
turbo-decoding message passing
array LDPC
block LDPC
irregular LDPC
semi-parallel architecture
Online Access:http://hdl.handle.net/1969.1/ETD-TAMU-1049
http://hdl.handle.net/1969.1/ETD-TAMU-1049

Internet

http://hdl.handle.net/1969.1/ETD-TAMU-1049
http://hdl.handle.net/1969.1/ETD-TAMU-1049

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