Throughput-Efficient Network-on-Chip Router Design with STT-MRAM
As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore systems. In designing efficient input buffers of NoC...
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| Format: | Others |
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2013
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| Online Access: | http://hdl.handle.net/1969.1/148157 |