PARALLEL DELAY FAULT GRADING HEURISTIC AND TESTING APPROACHES TO TROJAN IC DETECTION
A method to perform implicit path delay fault grading on GPGPU architectures is presented. Experimentally it is shown that it is over 1200x faster than a single-core implicit path delay fault grading method previously in the literature for higher accuracy and can be shown to scale to multiple GPGPU...
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| Format: | Others |
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OpenSIUC
2016
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| Online Access: | https://opensiuc.lib.siu.edu/dissertations/1315 https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=2319&context=dissertations |