SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. P...
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OpenSIUC
2009
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| Online Access: | https://opensiuc.lib.siu.edu/dissertations/291 https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=1291&context=dissertations |