Vertex Ordering for a Partitioning-based Fitting Algorithm for an EPLD Device
As the Application-Specific Integrated Circuit(ASIC) technology develops to the trend of high density and modulization, the ASIC device market has been dominated gradually by the more complex Erasable Programmable Logic Devices (EPLDs) and the Field Programmable Gate Array(FPGAs) instead of the ordi...
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| Format: | Others |
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PDXScholar
1993
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| Online Access: | https://pdxscholar.library.pdx.edu/open_access_etds/4585 https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=5656&context=open_access_etds |