Analog Implicit Functional Testing using Supervised Machine Learning

• Main Author: Bawaskar, Neerja Pramod
• Format: Others
• Published: PDXScholar 2014
• Subjects: Analog integrated circuits > Testing; Supervised learning (Machine learning) > Computer adaptive testing; Electrical and Computer Engineering
• Online Access: https://pdxscholar.library.pdx.edu/open_access_etds/2099; https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=3099&context=open_access_etds

Testing analog circuits is more difficult than digital circuits. The reasons for this difficulty include continuous time and amplitude signals, lack of well-accepted testing techniques and time and cost required for its realization. The traditional method for testing analog circuits involves measuring all the performance parameters and comparing the measured parameters with the limits of the data-sheet specifications. Because of the large number of data-sheet specifications, the test generation and application requires long test times and expensive test equipment. This thesis proposes an implicit functional testing technique for analog circuits that can be easily implemented in BIST circuitry. The proposed technique does not require measuring data-sheet performance parameters. To simplify the testing only time domain digital input is required. For each circuit under test (CUT) a cross-covariance signature is computed from the test input and CUT's output. The proposed method requires a training sample of the CUT to be binned to the data-sheet specifications. The binned CUT sample cross-covariance signatures are mapped with a supervised machine learning classifier. For each bin, the classifiers select unique sub-sets of the cross-covariance signature. The trained classifier is then used to bin newly manufactured copies of the CUT. The proposed technique is evaluated on synthetic data generated from the Monte Carlo simulation of the nominal circuit. Results show the machine learning classifier must be chosen to match the imbalanced bin populations common in analog circuit testing. For sample sizes of 700+ and training for individual bins, classifier test escape rates ranged from 1000 DPM to 10,000 DPM.