An integrated CMOS high precision time-to-digital converter based on stabilised three-stage delay line interpolation
Abstract This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact...
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| Format: | Doctoral Thesis |
| Language: | English |
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University of Oulu
2004
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| Online Access: | http://urn.fi/urn:isbn:951427461X http://nbn-resolving.de/urn:isbn:951427461X |