VHDL modeling and simulation of a digital image synthesizer for countering ISAR

VHDL modeling and simulation of a digital image synthesizer for countering ISAR

Approved for public release, distribution is unlimited === This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is m...

Full description

Bibliographic Details
Main Author: Kantemir, Ozkan
Other Authors: Fouts, Douglas J.
Format: Others
Published: Monterey, California. Naval Postgraduate School June
Subjects:
Image processing
Digital techniques
Electronic countermeasures
VHDL (Computer hardware description language)
Digital image synthesizer
DIS
VLSI
ASIC
CMOS
VHDL
Active HDLTM
Aldec
Tanner
Online Access:http://hdl.handle.net/10945/964

Internet

http://hdl.handle.net/10945/964

Similar Items