Architectural development and performance analysis of a primary data cache with read miss address prediction capability
This work is part of an ongoing effort to bridge the cycle time gap between high speed processing units and low speed main memories through the use of memory hierarchies. Cache memory exploits the principle of locality by providing a small, fast memory between the processor and the main memory. The...
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| Language: | en_US |
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Monterey, California. Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/32687 |