Planarity in ROMDD's of multiple-valued symmetric functions
An important consideration in the design of digital circuits is delay. A major source of delay in VLSI is interconnect. Crossings among interconnect require via's which cause resistance and additional delay. This thesis focuses on circuit design based on the reduced ordered multiple-valued deci...
| Main Author: | |
|---|---|
| Other Authors: | |
| Language: | en_US |
| Published: |
Monterey, California. Naval Postgraduate School
2013
|
| Online Access: | http://hdl.handle.net/10945/32192 |