Testing of a read prediction buffer integrated circuit and design of a predictive read cache
The objective of this research work was to evaluate and test the Read Prediction Buffer integrated circuit (IC). This IC attempts to decrease main- memory latency by predicting the next data cache read miss address and pre- fetching the data before the miss actually occurs in the cache. The motivati...
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| Language: | en_US |
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Monterey, California. Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/31512 |