Simulation and analysis of predictive read cache performance
Efforts to speed up the memory hierarchy have failed to keep up with the rapid increase in microprocessor performance. The use of first-level and second-level caches has become common in an effort to minimize this speed discrepancy. One potential method to overcome the speed problem while using much...
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| Language: | en_US |
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Monterey, California. Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/31469 |