Implementation of residue code as a design for testability strategy using GENESIL Silicon Compiler
Approved for public release; distribution unlimited. === This thesis describes the need for including design for testability in a VLSI chip design and provides information on implementing a DFT strategy using the GENESIL Silicon compiler. Two structured techniques of design for testability, Scan Des...
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Monterey, California: Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/27620 |