Python based FPGA design-flow
This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level l...
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| Format: | Dissertation |
| Language: | English |
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University of Cape Town
2016
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| Online Access: | http://hdl.handle.net/11427/20339 |