Power-efficient design methodology for video decoding.
As a proof of concept, the presented power-efficient design methodology is experimentally verified on a H.264/AVC baseline decoding system. A prototype chip is fabricated in UMC 0.18mum 1P6M standard CMOS technology. It is capable to decode H.264/AVC baseline profile of QCIF at 30fps. The chip conta...
| Other Authors: | |
|---|---|
| Format: | Others |
| Language: | English Chinese |
| Published: |
2007
|
| Subjects: | |
| Online Access: | http://library.cuhk.edu.hk/record=b6074499 http://repository.lib.cuhk.edu.hk/en/item/cuhk-344132 |