Program slicing for reliability and runahead in high level synthesis

• Main Author: Fleming, Shane
• Other Authors: Thomas, David
• Published: Imperial College London 2017
• Subjects: 621.3
• Online Access: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.745263

High-Level Synthesis (HLS) tools enable an FPGA circuit developer to trade performance for productivity by mapping a high-level circuit description into hardware. However, current HLS tools have limited support for fault-tolerance and memory management. This thesis addresses these issues by using a known software technique called program slicing to construct HLS optimisation passes. These optimisation passes use program slicing to create “slice circuits” that help the primary circuit at runtime. There are three main contributions in this thesis SliceUp, RELISH, and StitchUp. SliceUp is an API that can be used to create program slicing based HLS optimisation passes. The second is RELISH, an open source HLS optimisation pass that constructs an application specific prefetcher that can hide memory latency no matter how irregular the application’s access pattern. Both a theoretical and experimental analysis is performed on RELISH, showing that speedup is bounded between 1x – 2x and with experimental results in the range 1.02x – 1.69x. Finally, StitchUp is an open source HLS optimisation pass that builds a checker circuit that ensures the correct path is taken through the original circuit in the presence of soft-errors. This saves area over traditional approaches and reduces the number of false positives required for detection.