Program slicing for reliability and runahead in high level synthesis
High-Level Synthesis (HLS) tools enable an FPGA circuit developer to trade performance for productivity by mapping a high-level circuit description into hardware. However, current HLS tools have limited support for fault-tolerance and memory management. This thesis addresses these issues by using a...
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Imperial College London
2017
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| Online Access: | https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.745263 |