| Summary: | As minimum geometries of VLSI processes continue to shrink there have been two main effects on the field of parametric test. Firstly, structures must be able to characterise these smaller geometries and secondly the space for test structures has become more limited due to the requirement for them to be located in the scribe channel. The work of this thesis investigates methods of increasing the efficiency of test structure implementation to alleviate these problems. This work has demonstrated SPICE parameter extraction from test transistors accessed via a digitally addressed multiplexer: firstly using test circuits, to analyse pass transistor effects, then on a test chip using multiplexed access. The technique allows SPICE parameters to be extracted from transistor arrays with a large saving in the number of probe pads and hence overall silicon area. Digital misalignment structures have been implemented for the characterisation of small geometry processes. Use of such structures is demonstrated in this thesis using both a shift register output and a novel 'diode vernier' scheme. One of the main drawbacks of using shift register structures has been the requirement for a large amount of functional circuitry. The diode vernier introduced in this thesis is a simply designed structure that can be easily tested with standard parametric test equipment and requires only one diode per test structure element. Finally, a digital process control chip has been fabricated to integrate the ideas presented in this thesis. This uses multiplexers to access both test transistors and diode vernier structures. It demonstrates the feasibility of using a digital approach to parametric test chip design which has the potential to significantly reduce the area required for test structures.
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