Design and simulation of an MIMD shared memory multiprocessor with interleaved instruction streams
The design of the Epp1 MIMD shared memory multiprocessor is described, and its performance evaluated by simulation. The Epp1 has a dancehall architecture with <i>p</i> instruction interleaved RISC processors connected to <i>p</i> shared memories by a packet switched, combinin...
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University of Edinburgh
1991
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.662487 |