Methods and structures for characterising integrated circuit interconnect materials and processes

• Main Author: Shulver, Byron Jon Roderick
• Published: University of Edinburgh 2007
• Subjects: 621.3
• Online Access: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.661886

This thesis investigates a number of emerging areas in interconnect metrology with a connection on the use of electrical test structures to extract parameters such as line width, sheet resistance, and the overlay of multiple layers. To address the issue of calibrating optical overlay tools, a novel design for an overlay test structure is described for use as a reference material. It was developed to demonstrate the implementation of a technique devise in collaboration with researchers at NIST and allows the cross-correlation between measurements of overlay taken with electrical and optical techniques. The next proportion of this thesis presents a test structure to evaluate the emerging field of copper interconnects. It is designed to allow electrical measurements from all-copper features, and therefore removes the complications introduced by barrier materials. The process is then used to fabricate a test chip containing line widths form 10 to 0.55 <i>μ</i>m for the evaluation of various methods for ECD extraction. In this work, sheet resistance is extracted from three varieties of test structure designs with an investigation to support the results obtained. Following this, Kelvin-tapped bridge resistor structures are measured electrically to allow the line width to be determined. Three different approaches to analysing this parameter are examined and compared to line width values taken from SEM imaging. The final area of this work concentrates on the developing field of MEMS thick film power devices. An implementation of traditional interconnect test structures in thick copper conductive tracks is conducted to evaluate their potential for process and material characteristics. This was realised with the combination of thick film photo-resist processing and copper electroplating to fabricate the test structures. An algorithm is presented which permits values for line width to be extracted from Kelvin-tapped bridge resistors without the use of pre-determined sheet resistance values.