Circuit optimisation using device layout motifs
Circuit designers face great challenges as CMOS devices continue to scale to nano dimensions, in particular, stochastic variability caused by the physical properties of transistors. Stochastic variability is an undesired and uncertain component caused by fundamental phenomena associated with device...
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University of York
2015
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.659058 |