Dynamically reconfigurable network-on-chip
New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with Partial Dynamic Reconfiguration (PDR). The usage of a soft reconfigurable Network-on-Chip (NoC) to connect the...
| Main Author: | |
|---|---|
| Published: |
University of Bristol
2014
|
| Subjects: | |
| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.650099 |