Power minimisation techniques for testing low power VLSI circuits
Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI de...
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University of Southampton
2000
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| Online Access: | https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.561421 |