The effects of process variations on performance and robustness of bulk CMOS and SOI implementations of C-elements
Advances in semiconductor technology have been driven by the continuous demands of market forces for IC products with higher performance and greater functionality per unit area. To date industry has addressed these demands, principally, by scaling down device dimensions. However, several unintended...
Main Author: | Al Tarawneh, Ziyad |
---|---|
Published: |
University of Newcastle Upon Tyne
2011
|
Subjects: | |
Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.556031 |
Similar Items
-
Fabrication of strained and relaxed Si and SiGe by LPCVD for application in novel SOI technology
by: Bhattacharyya, S.
Published: (2004) -
Parasitic-aware design and layout for RF CMOS analogue integrated circuits
by: Zhu, Yongdong
Published: (2007) -
Ab initio scattering from random discrete charges and its impact on the intrinsic parameter fluctuations in nano-CMOS devices
by: Alexander, Craig L.
Published: (2005) -
Implementations of fault-tolerant quantum devices
by: Herrera-Marti, David A.
Published: (2012) -
Silicon carbide MEMS : characterisation and actuation of 3C-SiC cantilevers and bridges
by: Hassan, Musaab Abdalla
Published: (2006)