Linking the semantics of a multithreaded discrete event simulation language
Verilog is a hardware description language (HDL) that has been standardized and widely used in industry. MDESL is a Verilog-like language, which is a multithreaded discrete event simulation language. The language contains interesting features such as event-driven computation and sharedvariable concu...
| Main Author: | |
|---|---|
| Published: |
London South Bank University
2005
|
| Subjects: | |
| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.411142 |