Interconnection of transputer links using a multiple bus configuration
The design of an efficient distributed memory transputer network is a difficult issue. In order to construct successfully highly concurrent systems with a large number of processors, their interconnection networks have to be as universal as possible and provide adequate connectivity for most applica...
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University of Surrey
1992
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| Online Access: | https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.317380 |